Chinese Physics C > 2015, Vol. 39 > Issue(12): 126102 DOI: 10.1088/1674-1137/39/12/126102

Clock auto-synchronization method for BESIII ETOF upgrade

WANG Si-Yu^1,2,
CAO Ping^1,2,,,
LIU Shu-Bin^1,2,
AN Qi^1,2

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Abstract：
An automatic clock synchronization method implemented in a field programmable gate array (FPGA) is proposed in this paper. It is developed for the clock system which will be applied in the end-cap time of flight (ETOF) upgrade of the Beijing Spectrometer (BESIII). In this design, an FPGA is used to automatically monitor the synchronization circuit and deal with signals coming from the external clock synchronization circuit. By testing different delay time of the detection signal and analyzing the signal state returned, the synchronization windows can be found automatically by the FPGA. The new clock system not only retains low clock jitter which is less than 20ps root mean square (RMS), but also demonstrates automatic synchronization to the beam bunches. So far, the clock auto-synchronizing function has been working successfully under a series of tests. It will greatly simplify the system initialization and maintenance in the future.
- BESIII,
- endcap time-of-flight,
- clock synchronization

References

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WANG Si-Yu, CAO Ping, LIU Shu-Bin and AN Qi. Clock auto-synchronization method for BESIII ETOF upgrade[J]. Chinese Physics C, 2015, 39(12): 126102. doi: 10.1088/1674-1137/39/12/126102

WANG Si-Yu, CAO Ping, LIU Shu-Bin and AN Qi. Clock auto-synchronization method for BESIII ETOF upgrade[J]. Chinese Physics C, 2015, 39(12): 126102. doi:10.1088/1674-1137/39/12/126102 shu

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Received: 2015-03-10
Revised: 2015-06-01

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Supported by National Natural Science Foundation of China (10979003, 11005107), CAS Center for Excellence in Particle Physics (CCEPP)

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1.
沈阳化工大学材料科学与工程学院沈阳 110142

Clock auto-synchronization method for BESIII ETOF upgrade

Corresponding author:CAO Ping,

Received Date:2015-03-10
Accepted Date:2015-06-01
Available Online:2015-12-20

Fund Project:Supported by National Natural Science Foundation of China (10979003, 11005107), CAS Center for Excellence in Particle Physics (CCEPP)

Abstract:An automatic clock synchronization method implemented in a field programmable gate array (FPGA) is proposed in this paper. It is developed for the clock system which will be applied in the end-cap time of flight (ETOF) upgrade of the Beijing Spectrometer (BESIII). In this design, an FPGA is used to automatically monitor the synchronization circuit and deal with signals coming from the external clock synchronization circuit. By testing different delay time of the detection signal and analyzing the signal state returned, the synchronization windows can be found automatically by the FPGA. The new clock system not only retains low clock jitter which is less than 20ps root mean square (RMS), but also demonstrates automatic synchronization to the beam bunches. So far, the clock auto-synchronizing function has been working successfully under a series of tests. It will greatly simplify the system initialization and maintenance in the future.