The 2025 International Workshop on the High Energy Circular Electron Positron Collider

High-Energy Physics (HEP) experiments increasingly rely on complex ASICs, driving a growing need for flexible, programmable architectures. We present a RISC-V–based System-on-Chip (SoC) that serves as a versatile control and configuration hub for CEPC ASICs. The SoC integrates tiny_riscv, a lightweight 32-bit processor with a 3-stage pipeline, capable of executing C programs to manage registers and implement communication protocols such as I²C and SPI via firmware. Its application will first be demonstrated in LATRIC, an ASIC for Low-Gain Avalanche Diode (LGAD) readout, with fabrication planned in a 55 nm CMOS process in October. This talk will present the SoC design, its implementation for CEPC ASICs, and prospects for future development and applications.