Speaker
Description
Pioneering R&D in HVCMOS pixel sensors at the advanced 55 nm process, the COFFEE series prototypes are currently being developed for the CEPC inner tracker and Upstream Pixel tracker (UP) in the LHCb Upgrade II. COFFEE3, the latest prototype with two distinct readout architecture, was design and fabricated in 2025. Though featuring a small-scale prototype (3×4 mm2), COFFEE3 is designed to match the final full-scale sensor (~2×2 cm2), aiming for proof of concept. To ensure that COFFEE chip will be able to handle the particle hit density at both of the two applications, simulations of both readout architectures were performed. This is achieved by implementing, in C++, behavioral modeling of the pixel array and digital periphery, and then injecting Monte Carlo input data at the front-end to simulate realistic conditions. This talk will report the simulated efficiency of both readout architectures under full-scale array conditions, and the hit loss occurring during the process from the generation of hit information within the pixel to its readout to the end of column (EoC) buffers, caused by pile-up effects under high hit density of both the CEPC and the LHCb environment. One readout architecture demonstrates an efficiency exceeding 99% when the EoC's single read operation takes less than 100 ns. Beyond this, using the same methodology of C++ behavioral modeling combined with Monte Carlo data, we have optimized the arbitration algorithm to enable rational scheduling of transmission resources within the digital periphery, addressing UP's data compression format requirements and the bandwidth limitations of the chip's readout link. The outcomes of this work are intended to identify bottlenecks in on-chip data processing and transmission under the high hit-density environment, and to further optimize the chip architecture to satisfy the comprehensive performance requirements of these applications.
