Speaker
Description
Sub-100nm processes are becoming a critical trend in the development of HV-CMOS pixel detector technology. To evaluate the impact of in-pixel electronics design on HV-CMOS pixel sensor performance at these advanced process nodes, we have designed and submitted a prototype chip named COFFEE2, fabricated using a 55nm HV-CMOS process. This chip features a pixel array of 32 rows by 20 columns, divided into three regions, each with distinct in-pixel amplifier and comparator structures. Additionally, the chip includes a bandgap reference, row/column configurations, and digital-to-analog converters (DACs) integrated into the peripheral circuitry surrounding the pixel matrix. We will present detailed electronic designs, simulation results, and preliminary test results.
